Formal Digital Verification Engineer

We are seeking a Formal Digital Verification Engineer to join an innovative semiconductor company developing next-generation AI hardware and high-performance interconnect technology.

Formal Digital Verification Engineer

Location:Germany (Dortmund) (Hybrid)

About the Role

An innovative semiconductor company developing next-generation AI hardware is looking for a Formal Digital Verification Engineer to join their R&D team. The company focuses on building scalable, high-performance interconnect technology that enables high bandwidth, ultra-low latency, and improved power efficiency for AI infrastructure.

Key Responsibilities

• Develop and implement formal verification methodologies
• Participate in RTL design reviews
• Create verification plans based on design specifications
• Document results and coverage metrics for formal sign-off
• Maintain the verification environment and track/resolve design bugs
• Work closely with RTL design engineers on micro-architecture verification

Required Skills

• Strong experience in formal verification
• Knowledge of metrics-driven verification and coverage closure
• Experience with assertion-based languages (SVA or PSL)
• Scripting skills in Python, Perl, or TCL
• Strong debugging and analytical skills
• Experience with Cadence JasperGold and VManager preferred
• Understanding of instruction set architectures, interrupts, and bus architectures

Experience

• 5+ years in the semiconductor industry
• Experience verifying complex ASIC or FPGA designs
• Familiarity with SerDes or high-speed protocols (PCIe, USB, DP) is a plus
• Experience with UVM-based verification is advantageous

Education

• Bachelor’s degree in Electronics or Electrical Engineering (or higher)